Generation of High Power Test Vector Set for Combinational VLSI Circuits

Defence Science Journal

K.T. Oornmen Tharakan²  S.S.S.P. Rao¹ 

[1] Indian Institute of Technology Bombay, Mumbai;Vikram Sarabhai Space Centre, Thiruvananthapuram

关键词: Bum-in simulation;    latent defects;    failure mechanisms;    burn-in test vectors;    stress testing;    VLSI devices;    VLSI circuits;    CMOS signal switching;    power vectors;    algorithm;    CMOS gates;    CMOS device;    complementary metal oxide semiconductor device;   

DOI  :  

学科分类：社会科学、人文和艺术（综合）

来源: Defence Scientific Information & Documentation Centre

【 摘 要 】

"Burn-in is a well-known technique thathelps to accelerate failure mechanisms to surface out latent defects,which are not activated during normal testing of the VLSI devices. Thedevices are kept at a specified high temperature, for a specifiedperiod, in static or dynamic conditions. Since this method iscumbersome, an alternate method based on complementary metal oxidesemiconductor (CMOS) signal switching for VLSI devices is considered.The majority of power dissipation in CMOS circuitry is due to theswitching current associated with charging and discharging of loadcapacitances. Hence, if the test vectors can be so designed that maximumactivity is conjured, the stress on the device can be maximised. Inthis paper, a new algorithm for generation of these power vectors from agate-level description of the circuit is presented. The method has beenapplied to different circuits and the results compared.

【 授权许可】

Unknown