Carry select adder with sub-block power gating for reducing active-mode leakage in sub-32-nm VLSIs

IEICE Electronics Express

Chul-Moon Jung¹  Kyeong-Sik Min¹  Huan Minh Vo¹  Eun-Sub Lee¹ 

[1] School of Electrical Engineering, Kookmin University

关键词: low-leakage;    power gating;    sleep transistor;    active-mode power gating;    run-time power gating;   

DOI  :  10.1587/elex.8.1322

学科分类：电子、光学、磁材料

来源: Denshi Jouhou Tsuushin Gakkai

【 摘 要 】

References(8)In this paper, we propose the sub-block Active-Mode Power Gating (AMPG) scheme to reduce the active-mode leakage and apply it to the 32-bit Carry Select Adder (CSA), where the sub-blocks are activated and deactivated according to the idleness during the active time. By doing so, we can reduce the active-mode energy by 21% at the cycle time of 10ns for the 22-nm node compared to the conventional AMPG. The critical path delay is degraded as little as 1% in the sub-block AMPG. For a given power budget as small as 100µW, the new sub-block AMPG with 32-nm node can run faster by 47% than the conventional AMPG.

【 授权许可】

Unknown