Speeding-up exact and fast FIFO-based cache configuration simulation

IEICE Electronics Express

Masashi Tawada²  Masao Yanagisawa¹  Nozomu Togawa² 

[1] Dept. of Electronic and Photonic Systems, Waseda University;Dept. of Computer Science and Engineering, Waseda University

关键词: FIFO;    cache simulation;    cache memory;    cache configuration optimization;    embedded systems;   

DOI  :  10.1587/elex.8.1161

学科分类：电子、光学、磁材料

来源: Denshi Jouhou Tsuushin Gakkai

【 摘 要 】

References(6)The number of sets, block size, and associativity determine processor's cache configurations. Particularly in embedded systems, their cache configuration can be optimized since their target applications are much limited. Recently, the CRCB method has been proposed for LRU-based (Least Recently Used-based) cache configuration simulation, which can calculate cache hit/miss counts accurately and very fast changing the three parameters. However many recent processors use FIFO-based (First-In-First-Out-based) caches instead of LRU-based caches due to the viewpoints of their hardware costs. In this paper, we propose a speeding-up cache configuration simulation method for embedded applications that uses FIFO as a cache replacement policy. We first prove several properties for FIFO-based caches and then propose a simulation method that can process two or more FIFO-based cache configurations with different cache associativities simultaneously. Experimental results show that our proposed method can obtain accurate cache hits/misses and runs up to 32% faster than the conventional simulators.

【 授权许可】

Unknown