Efficiency optimization of charge pump circuit in NAND FLASH memory

IEICE Electronics Express

JunSeob Chung¹  BongSeok Han¹  DuckJu Kim¹  JeaGun Park²  SungWook Choi¹ 

[1] Flash Design Team I, Flash Development Division, Hynix Semiconductor Inc.;Nano SOI Process Laboratory, Room #101, HIT, Hanyang University

关键词: NAND FLASH;    charge pump;    efficiency;    current reduction;   

DOI  :  10.1587/elex.8.1343

学科分类：电子、光学、磁材料

来源: Denshi Jouhou Tsuushin Gakkai

【 摘 要 】

References(4)Cited-By(1)In this paper, power efficiency optimization scheme of charge pump circuit in NAND FLASH memory was proposed. The proposed scheme was implemented in program/erase charge pump by pump stage number control method. The maximum power efficiency of this pump is about 30%, and the maximum point is around 70% point of highest voltage level. So in this paper, to operate program/erase pump in highest power efficiency area, the pump stage number control scheme is proposed and evaluated in 20nm 64Gb MLC NAND FLASH memory circuit. Simulation result shows overall improvement of power efficiency, and at the wafer test about 10mA peak current reduction and overall improvement of power dissipation are found.

【 授权许可】

Unknown