IEICE Electronics Express | |
BIST design of power switch | |
Chen Xin1  Hu Wei1  Shan Weiwei2  Wu Ning1  | |
[1] College of Electronic and Information Engineering, Nanjing University of Aeronautics & Astronautics;National ASIC System Engineering Research Center, Southeast University | |
关键词: power switch; built-in self test (BIST); low power; | |
DOI : 10.1587/elex.10.20130469 | |
学科分类:电子、光学、磁材料 | |
来源: Denshi Jouhou Tsuushin Gakkai | |
【 摘 要 】
References(4)It is becoming common to implement power switches in low power system-on-chip (SoC). However, the power switches are not tested for manufactory defects in most designs currently. In this letter, a novel built-in self test (BIST) solution for power switch is proposed. The proposed solution can test the power switch with complete test vectors and fewer test cycles. For m switches, it only takes m+3 cycles to complete the whole test operation. Besides, the test vectors are very simple, the test results are very easy to be identified, and the proposed BIST circuit can be scaled freely with the amount of switches. In addition, although headers are analyzed in detail in this letter, the results are equally applicable to footers.
【 授权许可】
Unknown
【 预 览 】
Files | Size | Format | View |
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RO201911300899708ZK.pdf | 29KB | download |