On-Chip Implementation of Pipeline Digit-Slicing Multiplier-Less Butterfly for Fast Fourier Transform Architecture | Science Publications

American Journal of Engineering and Applied Sciences

Rozita Teymourzadeh¹  Mok V. Hong¹  Masuri Othman¹  Yazan S. Algnabi¹  Md S. Islam¹ 

关键词: Pipelined digit-slicing multiplier-less;    Fast Fourier Transform (FFT);    Verilog HDL;    Xilinx;   

DOI  :  10.3844/ajeassp.2010.757.764

学科分类：工程和技术（综合）

来源: Science Publications

【 摘 要 】

Problem statement: The need for wireless communication has driven the communicationsystems to high performance. However, the main bottleneck that affects the communication capabilityis the Fast Fourier Transform (FFT), which is the core of most modulators. Approach: This studypresented on-chip implementation of pipeline digit-slicing multiplier-less butterfly for FFT structure.The approach taken; in order to reduce computation complexity in butterfly, digit-slicing multiplierlesssingle constant technique was utilized in the critical path of Radix-2 Decimation In Time (DIT)FFT structure. The proposed design focused on the trade-off between the speed and active silicon areafor the chip implementation. The new architecture was investigated and simulated with MATLABsoftware. The Verilog HDL code in Xilinx ISE environment was derived to describe the FFT Butterflyfunctionality and was downloaded to Virtex II FPGA board. Consequently, the Virtex-II FG456 Protoboard was used to implement and test the design on the real hardware. Results: As a result, from thefindings, the synthesis report indicates the maximum clock frequency of 549.75 MHz with the totalequivalent gate count of 31,159 is a marked and significant improvement over Radix 2 FFT butterfly.In comparison with the conventional butterfly architecture, design that can only run at a maximumclock frequency of 198.987 MHz and the conventional multiplier can only run at a maximum clockfrequency of 220.160 MHz, the proposed system exhibits better results. The resulting maximum clockfrequency increases by about 276.28% for the FFT butterfly and about 277.06% for the multiplier.Conclusion: It can be concluded that on-chip implementation of pipeline digit-slicing multiplier-lessbutterfly for FFT structure is an enabler in solving problems that affect communications capability inFFT and possesses huge potentials for future related works and research areas.

【 授权许可】

Unknown