A low-cost FPGA implementation of multi-channel FIR filter with variable bandwidth

IEICE Electronics Express

Sang Yoon Park¹ 

[1] Department of Electronic Engineering and MPEES-ARC, Myongji University

关键词: FIR filter;    multi-channel;    FPGA;    reconfigurable;    low-cost;    variable bandwidth;   

DOI  :  10.1587/elex.12.20150702

学科分类：电子、光学、磁材料

来源: Denshi Jouhou Tsuushin Gakkai

【 摘 要 】

References(13)This paper proposes a low-cost implementation of a multi-channel FIR filter on FPGA, where each channel can have variable bandwidth and coefficients. New structures of the tapped-delay line and the coefficient bank unit based on time-division multiplexing are proposed. Pipelined adder tree is used to expedite the filtering process without disturbing generation of control signals for multi-channel data access. From implementation results, it is found that the proposed 39-tap FIR filter involves 32% less number of slice registers as well as 65% less number of DSP blocks than the Xilinx FIR Core 5.0, and also supports variable bandwidth.

【 授权许可】

Unknown