VLSI Implementation of Novel Class of High Speed Pipelined Digital Signal Processing Filter for Wireless Receivers | Science Publications

American Journal of Engineering and Applied Sciences

Rozita Teymourzadeh¹  Jimmy M.V. Hong¹  Masuri Othman¹  Yazan S. Algnabi¹  Md S. Islam¹ 

关键词: ASIC;    CIC;    CMOS;    FPGA;    sigma delta modulator;    silterra;    virtex;    Xilinx;   

DOI  :  10.3844/ajeassp.2010.663.669

学科分类：工程和技术（综合）

来源: Science Publications

【 摘 要 】

Problem statement: The need for high performance transceiver with high Signal to NoiseRatio (SNR) has driven the communication system to utilize latest technique identified as oversampling systems. It was the most economical modulator and decimation in communication system. Ithas been proven to increase the SNR and is used in many high performance systems such as in theAnalog to Digital Converter (ADC) for wireless transceiver. Approach: This research presented thedesign of the novel class of decimation and its VLSI implementation which was the sub-component inthe over sampling technique. The design and realization of main unit of decimation stage that was theCascaded Integrator Comb (CIC) filter, the associated half band filters and the droop correction arealso designed. The Verilog HDL code in Xilinx ISE environment has been derived to describe theproposed advanced CIC filter properties. Consequently, Virtex-II FPGA board was used to implementand test the design on the real hardware. The ASIC design implementation was performed accordinglyand resulted power and area measurement on chip core layout. Results: The proposed designfocused on the trade-off between the high speed and the low power consumption as well as thesilicon area and high resolution for the chip implementation which satisfies wireless communicationsystems. The synthesis report illustrates the maximum clock frequency of 332 MHz with the activecore area of 0.308

【 授权许可】

Unknown