IEICE Electronics Express | |
Express Ring: a multi-layer and non-blocking NoC architecture | |
Peng Wang1  Chen Li1  Yang Guo1  Shenggang Chen1  Sheng Ma1  | |
[1] College of Computer, National University of Defense Technology | |
关键词: NoC; Ring; multi-layer; non-blocking; global signal; | |
DOI : 10.1587/elex.12.20141190 | |
学科分类:电子、光学、磁材料 | |
来源: Denshi Jouhou Tsuushin Gakkai | |
【 摘 要 】
References(14)As the Network-on-Chip (NoC) induces significant hardware overheads, it becomes the performance and scalability bottleneck of System-on-Chip (SoC) design. To address this challenge, we propose a multi-layer, non-blocking ring NoC architecture. Multi-layer links with different bandwidth achieve high link utilization and avoid protocol-level deadlock. The non-blocking architecture leverages bufferless router to reduce hardware overheads and simplifies router pipeline to reduce zero-load latency. We also propose a scalable global signal control mechanism to eliminate the starvation and avoid the loss of packets. Compared with the conventional ring network composed of dateline routers (DRing) and Intel Nehalem-EX ring network (NRing), our design achieves 69.4% and 12.3% performance improvements, respectively. Compared with DRing, it also reduces hardware overheads.
【 授权许可】
Unknown
【 预 览 】
Files | Size | Format | View |
---|---|---|---|
RO201911300790752ZK.pdf | 3441KB | download |