A 2/5mW CMOS ΔΣ modulator employed in an improved GSM/UMTS receiver structure

IEICE Electronics Express

A. Zahabi¹  O. Shoaei¹  P. Jabehdar-maralani¹  Y. Koolivand¹ 

[1] IC Design Laboratory, University of Tehran

关键词: Delta-Sigma modulator;    Capacitor spread;    Dual-quantizer;   

DOI  :  10.1587/elex.2.267

学科分类：电子、光学、磁材料

来源: Denshi Jouhou Tsuushin Gakkai

【 摘 要 】

References(3)Cited-By(1)In this paper, the design of a reconfigurable low-power low-pass Switched Capacitor Delta-Sigma (SC ΔΣ) modulator for GSM/UMTS standards used in an optimum low-IF(LIF)/Zero-IF(ZIF) receiver architecture is described. A new approach for obtaining the optimum modulator coefficients is developed which results in relaxed specifications of the circuit components, aggressive noise transfer function (NTF) and a signal transfer function (STF) with the blocker-rejection property. The modulator employs a second/third-order single-stage dual-quantizer structure. It achieves 85.6dB/57dB SNDR and -0.2dBFS/-0.05dBFS overload factor at 0.2/2MHz bandwidth for GSM/UMTS standards and consumes only 2mW/5mW from a single 1.8V supply in a 0.18µm 1P6M CMOS process. The maximum spread of the modulator capacitors is 105.

【 授权许可】

Unknown