A comprehensive metering scheme for intellectual property protection during both after-sale and evaluation periods of IC design

IEICE Electronics Express

Wenjie Che¹  Yaping Lin¹  Yonghe Liu¹  Jinguo Li¹  Aobo Pan¹  Zhiqiang You¹ 

[1] College of Information Science and Engineering, Hunan University

关键词: intellectual property protection (IPP);    IC design;    hardware metering;    finite state machine (FSM);    physically unclonable function (PUF);   

DOI  :  10.1587/elex.10.20130649

学科分类：电子、光学、磁材料

来源: Denshi Jouhou Tsuushin Gakkai

【 摘 要 】

References(24)In this paper, we propose a comprehensive scheme that simultaneously achieves IP protection in both after-sale and evaluation periods. Our key idea is to build a pre-verification path into an active metering structure, with a non-functional defect purposely attached to the path, rendering any potential pirating users unwilling to risk the defective behavior of the fabricated chips. Using the MCNC’91 benchmarks, we achieve a large area-to-power ratio proving the feasibility of our scheme. At the same time, compared with a well-known metering scheme, the proposed scheme can significantly improve the robustness against brute-force attack, roughly by an average value of 27.4 per layer. The scheme can also reduce the area and power overhead by 4.4% and 11.2% on average considering an extra 5 to 10 layers.

【 授权许可】

Unknown