Two-parallel Reed-Solomon based FEC architecture for optical communications

IEICE Electronics Express

Chang-Seok Choi¹  Seungbeom Lee¹  Hanho Lee¹ 

[1] School of Information and Communication Engineering, Inha University

关键词: Reed-Solomon code;    forward error correction;    two-parallel;   

DOI  :  10.1587/elex.5.374

学科分类：电子、光学、磁材料

来源: Denshi Jouhou Tsuushin Gakkai

【 摘 要 】

References(5)Cited-By(6)This paper presents a high-speed Forward Error Correction (FEC) architecture based on two-parallel Reed-Solomon (RS) decoder for 10 and 40-Gb/s optical communication systems. A high-speed two-parallel RS(255, 239) decoder has been proposed and the derived structure can also be applied to implement the 10 and 40-Gb/s RS FEC architectures. The implementation results show that 16-Ch. RS FEC architecture can operate at a clock frequency of 160MHz and has a throughput of 41Gb/s for the Xilinx Virtex4 FPGA. Also, RS FEC operates at a clock frequency of 400MHz and has a throughput of 102Gb/s for 0.18-µm CMOS technology.

【 授权许可】

Unknown