Low-power dual-supply clock networks with clock gating and frequency doubling

IEICE Electronics Express

Jae Cheol Son¹  Jong-Woo Kim²  Bai-Sun Kong²  Hoi-Jin Lee²  Tae Hee Han²  Jeong-Taek Kong³ 

[1] SOC Team, System LSI Division, Samsung Electronics;School of Inform. and Comm. Eng., Sungkyunkwan University;Samsung Semiconductor Institute of Technology, Samsung Electronics

关键词: dual supply;    clock gating;    level converting;    clock distribution;   

DOI  :  10.1587/elex.9.502

学科分类：电子、光学、磁材料

来源: Denshi Jouhou Tsuushin Gakkai

【 摘 要 】

References(5)Low-power dual-supply clock networks based on novel level-converting clock gating cells are presented. The proposed clock networks achieve a substantial power saving with mitigated timing constraints on gated clocks. They also allow pulse-based flip-flops used at leaf clock nodes to work with no pulse generators, resulting in more power saving and area reduction. The proposed dual-supply clock networks were designed in a 32nm CMOS technology. The evaluation results indicated that the proposed clock-gating cells have up to 24.8% smaller power with 74.3% reduced latency and 17.5% reduced area. They also indicate that the power consumption of the proposed clock networks was reduced by up to 30.3%.

【 授权许可】

Unknown