Novel FPGA-based pipelined floating point FFT processor

IEICE Electronics Express

Wang Jun¹  Li Wei¹ 

[1] School of Electronics and Information Engineering, Beijing University of Aeronautics and Astronautics

关键词: FFT;    pipelined;    floating point;    FPGA;   

DOI  :  10.1587/elex.7.268

学科分类：电子、光学、磁材料

来源: Denshi Jouhou Tsuushin Gakkai

【 摘 要 】

References(8)Two novel architectures for pipelined floating point fast Fourier transform on FPGA are presented. The new radix-22 two-path delay feedback (R22TDF) architecture leads to 50% area saving for floating point complex adders compared with the radix-22 single-path delay feedback (R22SDF) architecture. Besides a new hybrid architecture is presented which mixes the R22TDF and R22TDF butterfly structures and is flexible and efficient for FPGA implementation.

【 授权许可】

Unknown