| IEICE Electronics Express | |
| Time-distributed procedure for fast estimation of effective number of bits during ADC Design | |
| Siou-Wei Su1  Wei-Liang Lin1  Shing-Yan Liang1  Chen-Hao Chang1  Zhi-Xun Liu1  | |
| [1] Department of Electrical Engineering, National Chung Hsing University | |
| 关键词: effective number of bits; analog-to-digital converter; successive approximation register ADC; | |
| DOI : 10.1587/elex.8.1703 | |
| 学科分类:电子、光学、磁材料 | |
| 来源: Denshi Jouhou Tsuushin Gakkai | |
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【 摘 要 】
References(5)This work proposes and analyzes an intuitive time-distributed procedure for estimating the effective number of bits (ENOB) of ADCs during the design phase. Two derived numbers, the ENOB lower-bound and the ENOB upper-bound, signal to a designer whether the design has satisfied the desired quality, or either further circuit improvement or a more accurate time-distributed procedure is necessary. The result enables designers to employ the procedure to almost linearly reduce the ENOB simulation waiting time with a controllable loss of accuracy. Two successive approximation register (SAR) ADC designs demonstrate the effectiveness of the procedure, one of which has been manufactured.
【 授权许可】
Unknown
【 预 览 】
| Files | Size | Format | View |
|---|---|---|---|
| RO201911300648444ZK.pdf | 364KB |
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