A high speed modulo (2n �? 2p + 1) multiplier design

IEICE Electronics Express

Lei Li¹  Qyu Zhang¹  Hai Yan¹ 

[1] Research Institute of Electronic Science and Technology, University of Electronic Science and Technology of China

关键词: residue number systems (RNS);    multiplier;   

DOI  :  10.1587/elex.12.20150870

学科分类：电子、光学、磁材料

来源: Denshi Jouhou Tsuushin Gakkai

【 摘 要 】

References(10)In this express, an optimized architecture for modulo (2n �? 2p + 1) multipliers is proposed. Compared with the state-of-art, synthesized results demonstrate that the proposed multipliers can achieve an average delay savings of about 11.8%. With the increase of n, the average delay savings also increases remarkably.

【 授权许可】

Unknown