A 3.5mW 5µsec settling time dual-band fractional-N PLL synthesizer

IEICE Electronics Express

Jun Gyu Lee¹  Shoichi Masui¹ 

[1] Research Institute of Electrical Communication, Tohoku University

关键词: phase locked loop;    low power design;    voltage controlled oscillator;   

DOI  :  10.1587/elex.9.307

学科分类：电子、光学、磁材料

来源: Denshi Jouhou Tsuushin Gakkai

【 摘 要 】

References(8)We explore a dual-band fractional-N PLL synthesizer with 3.5mW, 5µsec settling time and 15µsec start-up time in 0.18µm CMOS technology. The power consumption is minimized through the design efforts in LC-VCO design to maximize the quality factor of an integrated inductor up to 6.1 at 866MHz and minimize the VCO gain by a capacitor tuning technique with an on-chip nonvolatile memory and the proper choice of varactor. Measured results of a prototype fractional-N PLL satisfy the required settling and start-up times, and indicate that the phase noises at 10kHz and 100KHz offset are -108.7dBc/Hz and -98.3dBc/Hz, respectively, and the reference spurious level is -81.6dBc.

【 授权许可】

Unknown