A novel delay optimization method for a critical path in VLSI design

IEICE Electronics Express

Guican Chen¹  Xiaolong Ma¹  Jiangtao Xu¹  Minshun Wu¹ 

[1] School of Electronics and Information Engineering, Xi’an Jiaotong University

关键词: critical path;    fan-out factor;    path delay;    VLSI;   

DOI  :  10.1587/elex.10.20130446

学科分类：电子、光学、磁材料

来源: Denshi Jouhou Tsuushin Gakkai

【 摘 要 】

References(4)This paper presents a new method for optimizing the delay of a critical path with an embeded long wire for global routing. And an appropriate effective fan-out factor (EFOF) for optimizing the sizes of the devices in the critical path is derived. Simulations show that the new optimization method can obtain more accurate delay estimation for a critical path than traditional method, which offers significant result for automatic floor-plan and routing in VLSI design.

【 授权许可】

Unknown