Cluster mesh: a topology for three-dimensional network-on-chip

IEICE Electronics Express

Huaxi Gu²  Junhui Wang²  Yintang Yang¹ 

[1] Institute of Microelectronics, Xidian University;State Key Laboratory of ISN, Xidian University

关键词: network-on-chip;    three-dimensional topology;    interconnection network;    through-silicon via;   

DOI  :  10.1587/elex.9.1254

学科分类：电子、光学、磁材料

来源: Denshi Jouhou Tsuushin Gakkai

【 摘 要 】

References(9)Cited-By(4)Three-dimensional network-on-chip (3D NoC) is a promising method to overcome the bottlenecks in 3D integrated circuit (IC). Although 3D NoC can provide more efficient inter-layer communication with through-silicon vias (TSVs), the low yield and high overhead become the main challenges. To obtain a balance point between cost and performance, the cluster mesh we proposed applies a new vertical interconnects squeezing scheme which decreases the amount of TSV by sharing vertical links through vertical routers. The simulation results show that the proposed topology can improve the yield of chip, reduce the overhead and provide acceptable performance.

【 授权许可】

Unknown