High performance sparse matrix-vector multiplication on FPGA

IEICE Electronics Express

Shice Ni¹  Song Guo¹  Yong Dou¹  Dan Zou¹ 

[1] National Laboratory for Parallel and Distributed Processing, National University of Defense Technology

关键词: FPGA;    sparse matrix-vector multiplication;    reconfigurable computing;    multi-channel memory;   

DOI  :  10.1587/elex.10.20130529

学科分类：电子、光学、磁材料

来源: Denshi Jouhou Tsuushin Gakkai

【 摘 要 】

References(7)Cited-By(2)This paper presents the design and implementation of a high performance sparse matrix-vector multiplication (SpMV) on field-programmable gate array (FPGA). By proposing a new storage format to compress the indexes of non-zero elements by exploiting the substructure of the sparse matrix, our SpMV implementation on a reconfigurable computing platform with a multi-channel memory subsystem is capable of obtaining similar performance by using a single FPGA to that of a highly optimized BFS implementation on a commercial heterogeneous system containing four FPGAs.

【 授权许可】

Unknown