On the efficient computation of single-bit input word length pipelined FFTs

IEICE Electronics Express

Saima Athar¹  Oscar Gustafsson¹  Fahad Qureshi¹  Izzet Kale² 

[1] Department of Electrical Engineering Linköping University;Applied DSP and VLSI Research Group University of Westminster

关键词: FFT algorithm;    complexity;    single-bit;    word length;   

DOI  :  10.1587/elex.8.1437

学科分类：电子、光学、磁材料

来源: Denshi Jouhou Tsuushin Gakkai

【 摘 要 】

References(7)This letter describes an efficient architecture for the computation of fast Fourier transform (FFT) algorithms with single-bit input. The proposed architecture is aimed for the first stages of pipelined FFT architectures, processing one sample per clock cycle, hence making it suiable for real-time FFT computation. Since natural input order pipeline FFTs use large memories in the early stages, it is important to keep the word length shorter in the beginning of the pipeline. By replacing the initial butterflies and rotators of an architecture with that of the proposed block, the memory requirements can be significantly reduced. Comparisons with the commonly used single delay feedback (SDF) architecture show that more than 50% of the required memory can be saved in some cases.

【 授权许可】

Unknown