| IEICE Electronics Express | |
| Elixir: A new bandwidth-constrained mapping for Networks-on-chip | |
| Ahmad Khademzadeh1  Midia Reshadi2  Akram Reza2  | |
| [1] Iran Telecommunication Research Center;Islamic Azad University, Science and Research Branch | |
| 关键词: Networks-on-chip; mapping; communication cost; bandwidth constrains; power consumption; average network latency; | |
| DOI : 10.1587/elex.7.73 | |
| 学科分类:电子、光学、磁材料 | |
| 来源: Denshi Jouhou Tsuushin Gakkai | |
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【 摘 要 】
References(17)Cited-By(6)Nowadays, with technology shrinking and the huge demand for supporting multiple applications has led designers to use multiple IP cores within a single chip. Therefore, the designers have proposed Networks-on-chip to overcome the problems of future complex systems. Mapping IPs directly affects NoC design parameters such as latency and power consumption. In this paper we present a power and performance aware mapping technique based on the combination of both the bandwidth-constrained and branch and bound concepts. Results have shown improvements of the latency and power consumption of our technique when compared to other popular NoC mappings.
【 授权许可】
Unknown
【 预 览 】
| Files | Size | Format | View |
|---|---|---|---|
| RO201911300521722ZK.pdf | 1050KB |
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