A counter-based all-digital spread-spectrum clock generator with high EMI reduction in 65nm CMOS

IEICE Electronics Express

Ching-Che Chung²  Wei-Da Ho²  Duo Sheng¹ 

[1] Department of Electrical Engineering, Fu Jen Catholic University;Department of Computer Science & Information Engineering, National Chung-Cheng University

关键词: EMI reduction;    ADPLL;    SSCG;   

DOI  :  10.1587/elex.10.20130090

学科分类：电子、光学、磁材料

来源: Denshi Jouhou Tsuushin Gakkai

【 摘 要 】

References(6)An all-digital spread-spectrum clock generator (ADSSCG) with direct modulation on the digitally controlled oscillator (DCO) is presented. The proposed ADSSCG can generate an accurate triangular modulation on the output frequency, and thus it can achieve high electromagnetic interference (EMI) reduction with a smaller spreading ratio as compared with existing designs. In addition, the proposed frequency counter-based mechanism can maintain the long-term frequency stability of the ADSSCG. The proposed ADSSCG is implemented in a standard performance 65nm CMOS process, the active area is 85μm × 85μm. It consumes 163.9μW at 270MHz with a 1.0V power supply. The EMI reduction of the proposed ADSSCG is 13.99dB with a 0.5% spreading ratio at 270MHz, and 20.23dB EMI reduction is achieved with a 1.5% spreading ratio at 162MHz. Moreover, the proposed ADSSCG is designed with standard cells, and thus it can be ported to different process in a short time.

【 授权许可】

Unknown