A 2-bit/step SAR ADC structure with one radix-4 DAC

IEICE Electronics Express

M. B. Ghaznavi-Ghoushchi¹  M. H. M. Larijani¹ 

[1] School of Engineering, Shahed University

关键词: successive approximation;    2-bit/step SAR ADC;    radix-4 DAC;   

DOI  :  10.1587/elex.9.840

学科分类：电子、光学、磁材料

来源: Denshi Jouhou Tsuushin Gakkai

【 摘 要 】

References(4)In this letter, a high speed compact structure for 2-bit/step successive approximation (SAR) ADC is presented. Using modified algorithm yields to a simple radix-4 DAC with half bit and a resolution independent Reference Generator unit in the proposed design. This in term caused to extend the resolution of SAR ADC structure for double bit resolutions. An 8-bit SAR ADC is implemented and simulated based on the proposed structure in 300MHz clock frequency and 50MS/s sampling rate. The target design has SNDR=43dB and SFDR=52dB for fin=4MHz at 50Ms/s. The achieved power consumption at this sampling rate is 1.04mW and the Figure of Merits of proposed design will be 175fJ/Conversion-step.

【 授权许可】

Unknown