| IEICE Electronics Express | |
| Systematic design method for low power, high speed LTPS TFT based CML inverter/buffer | |
| Ju Young JEONG1  | |
| [1] Department of Electronic Engineering, The University of Suwon | |
| 关键词: system-on-panel; current mode logic; display; TFT; | |
| DOI : 10.1587/elex.4.531 | |
| 学科分类:电子、光学、磁材料 | |
| 来源: Denshi Jouhou Tsuushin Gakkai | |
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【 摘 要 】
References(5)Progress in LTPS TFT technology enabled the system-on-panel to prevail in small FPDs. And high speed TFT circuit technique is essential for expanding the system-on-panel applications. In this work, all p-channel, LTPS TFT, current mode inverter/buffer is introduced. To overcome the power hungry nature of the current mode circuit, small logic swing, complementary input, and systematic design method have been developed. The design method is essential tool to obtain the best trade off between power and delay. It is proved that the CML inverter/buffer can be designed to consume less power and to operate at higher speed than CMOS inverter.
【 授权许可】
Unknown
【 预 览 】
| Files | Size | Format | View |
|---|---|---|---|
| RO201911300427731ZK.pdf | 242KB |
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