IEICE Electronics Express | |
Design and implementation of a mixed-signal Boost converter with a novel multi-phase clock DPWM | |
Ke Wang1  Li Geng1  Shiquan Fan1  | |
[1] School of Electronics and Information Engineering, Xi′an Jiaotong University | |
关键词: DPWM; time-multiplexing; Boost converter; FPGA; | |
DOI : 10.1587/elex.7.1091 | |
学科分类:电子、光学、磁材料 | |
来源: Denshi Jouhou Tsuushin Gakkai | |
【 摘 要 】
References(5)There exists a trade-off among resolution, area and power losses in controllers of switching DC-DC converters. In this letter, a mixed-signal Boost converter topology is presented to lower the resolution requirements of ADC and DPWM. In addition, by using time-multiplexing technology, a novel multi-phase clock DPWM is proposed. Design Compiler synthesis results indict that, compared with normal 1-phase clock DPWM, chip area and power consumption of the proposed 4-phase clock DPWM is reduced by 47.0% and 54.4%, respectively. The new DPWM is realized using FPGA and applied in a prototype Boost converter. Experimental results verify the functionality of the optimized DPWM.
【 授权许可】
Unknown
【 预 览 】
Files | Size | Format | View |
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RO201911300401412ZK.pdf | 671KB | download |