DESIGN OF 8-4 AND 9-4 COMPRESSORS FORHIGH SPEED MULTIPLICATION | Science Publications

American Journal of Applied Sciences

Dhruv Bansal¹  R. Marimuthu¹  P. S. Mallick¹  S. Balamurugan¹ 

关键词: Binary Multiplier;    Compressors;    High Speed Adder;    Area Efficient;    Energy Delay Product;   

DOI  :  10.3844/ajassp.2013.893.900

学科分类：自然科学（综合）

来源: Science Publications

【 摘 要 】

This study presents higher order compressors which can be effectively used for high speed multiplications. The proposed compressors offer less delay and area. But the Energy Delay Product (EDP) is slightly higher than lower order compressors. The performance of 8×8, 16×16 and 24×24 multipliers using the proposed higher order compressors has been compared with the same multipliers using lower order compressors and found that the new structures can be used for high speed multiplications. These compressors are simulated with Cadence RTL complier at a temperature of 25°C with the supply voltage of 1.2 V.

【 授权许可】

Unknown