A 54-mw 3×-real-time 60-kword continuous speech recognition processor VLSI

IEICE Electronics Express

Masahiko Yoshimoto¹  Hiroshi Kawaguchi¹  Shintaro Izumi¹  Yuki Miyamoto¹  Kumpei Matsuda¹  Guangji He¹ 

[1] Department of Information Science, Kobe University

关键词: speech recognition;    VLSI;    low-power;   

DOI  :  10.1587/elex.10.20130787

学科分类：电子、光学、磁材料

来源: Denshi Jouhou Tsuushin Gakkai

【 摘 要 】

References(11)This paper describes a low-power VLSI chip for speaker-independent 60-kWord continuous speech recognition. We implement parallel and pipelined architecture for GMM computation and Viterbi processing. It includes a 8-path Viterbi transition architecture to maximize the processing speed and adopts tri-gram language model to improve the recognition accuracy. A two-level cache architecture is implemented for the demo system. Measured results show that our implementation achieves 25% required frequency reduction (62.5MHz) and 26% power consumption reduction (54.8mW) for 60k-Word real-time continuous speech recognition compared to the previous work. This chip can maximally process 3.02× and 2.25× times faster than real-time at 200MHz using the bigram and trigram language models, respectively.

【 授权许可】

Unknown