A compact Verilog-A model for Multi-Level-Cell Phase-change RAMs

IEICE Electronics Express

Kyeong-Sik Min¹  Ji-Hye Bong¹  Sung-Mo (Steve) Kang²  Kwan-Hee Jo¹ 

[1] School of Electrical Engineering, Kookmin University;School of Engineering, University of California, Merced

关键词: Phase Change RAMs;    Verilog-A model;    macromodel;    Multi Level Cell;    resistive memories;   

DOI  :  10.1587/elex.6.1414

学科分类：电子、光学、磁材料

来源: Denshi Jouhou Tsuushin Gakkai

【 摘 要 】

References(8)Cited-By(6)A new compact but accurate Verilog-A model for Multi-Level-Cell Phase-change RAMs is proposed in this paper. The previous circuit-based SPICE macromodel has to have a very complicated circuit to describe multi-level resistance thus it needs a long simulation time and occupies large computer memories. This new Verilog-A model can easily model the multi-level resistance by using the partial SET and RESET states where PCRAM resistance changes continuously without having a complicated circuit-based macromodel. Moreover, this new model is more portable, reliable, and simpler than the traditional C-based SPICE model owing to the advantage of Verilog-A. The new model has been compared with the measurement and proved to have good agreement with the measurement.

【 授权许可】

Unknown