Prototyping design of a flexible DSP block with pipeline structure for FPGA

IEICE Electronics Express

Jinmei Lai¹  Jian Wang¹  Hanyang Xu¹ 

[1] ASIC and System State Key Laboratory, Fudan University

关键词: DSP;    compressor;    pipeline;    FPGA;   

DOI  :  10.1587/elex.13.20160676

学科分类：电子、光学、磁材料

来源: Denshi Jouhou Tsuushin Gakkai

【 摘 要 】

References(17)Embedded hard DSP block effectively improves FPGA performance for arithmetic circuits. This paper proposes a novel DSP architecture. By adopting a new Compressor Array, the proposed DSP can additionally supports multi-operand addition which current commercial devices do not support. This makes the DSP block more versatile to cover a wider range of applications. But supporting multi-operand addition will significantly increase routing congestion. To alleviate timing degeneration caused by the more congestion routing, we implement a pipelined design in the Compressor Array. The proposed DSP block is fabricated in 1P10M 65 nm bulk CMOS process, Test results show a 53.7% reduction in critical path delay compared to the Field Programmable Compressor Tree (FPCT).

【 授权许可】

Unknown