A low cost test pattern generator for test-per-clock BIST scheme

IEICE Electronics Express

Zhen Wang¹  Feng Liang¹  Zeye Liu¹  Shaochong Lei¹ 

[1] School of Electronics and Information, Xi'an Jiaotong University

关键词: Built-in self-test;    test-per-clock;    test pattern generation;    single input change;    low power;   

DOI  :  10.1587/elex.7.672

学科分类：电子、光学、磁材料

来源: Denshi Jouhou Tsuushin Gakkai

【 摘 要 】

References(8)Test power and test overhead are crucial to VLSI and SOC testing. This paper proposes a low cost test pattern generator (TPG) for test-per-clock built-in self-test (BIST) scheme. The proposed method utilizes a two-dimensional TPG and a bit-XOR array to reduce area overhead, and generates single input change (SIC) sequences to reduce input transitions of the circuit under test (CUT). Simulation results on ISCAS benchmarks demonstrate that the proposed method can achieve high fault coverage and effectively reduce test power.

【 授权许可】

Unknown