Low latency, glitch-free booth encoder-decoder for high speed multipliers

IEICE Electronics Express

Amir Fathi¹  Habib Ghasemizadeh Tamar¹  Sarkis Azizian¹  Rahim Fathi¹ 

[1] Department of Electrical Engineering, Urmia branch, Islamic Azad University

关键词: booth encoder;    booth decoder;    multiplier;   

DOI  :  10.1587/elex.9.1335

学科分类：电子、光学、磁材料

来源: Denshi Jouhou Tsuushin Gakkai

【 摘 要 】

References(11)This paper is about the implementation of a novel booth encoder-decoder in a 0.35µm CMOS technology. By introducing a new truth table, the gate level delay from inputs to partial products is reduced to two XOR logic gates plus one transistor which is the main advantage of the proposed architecture. Also, the gate count is reduced which reduces the power dissipation. In addition, because of similar paths from inputs to outputs, the latency for all paths becomes equal. Therefore, the output waveforms will be free of glitch. Post layout simulations demonstrate that the delay of the whole system is 350ps.

【 授权许可】

Unknown