An Iterative Method for Algorithms Implementation on a Limited Dynamically Reconfigurable Hardware | Science Publications

Journal of Computer Science

Elbey Bourennane¹  Abdellatif Mtibaa¹  Lotfi Boussaid¹  Abdessalem B. Abdelali¹ 

关键词: Reconfigurable hardware;    run time reconfiguration;    time partitioning;    design points;   

DOI  :  10.3844/jcssp.2006.422.430

学科分类：计算机科学（综合）

来源: Science Publications

【 摘 要 】

In this study we propose a framework and a combined temporal partitioning and design space exploration method for run time reconfigurable processors. Our objective is to help designers to implement an algorithm in limited FPGA area resources while respecting the execution time constraint. The algorithm to be implemented is represented by a task graph with different implementation alternatives (design points) for each task. We study the effect of hardware resources limitation in the choice of the algorithm implementation design point. The proposed method is based on an heuristic technique which consists on combining temporal partitioning and task design points selection to obtain solutions that satisfy the imposed constraints.

【 授权许可】

Unknown