Synchronous delay based UWB pulse generator in FPGA

IEICE Electronics Express

Johan Bauwelinck²  Xiao Li²  Stephanie Teughels¹  Peter Vaes¹  Jan Vandewege²  Punithavathi Duraiswamy² 

[1] PEPRIC NV;Ghent University, INTEC/IMEC

关键词: UWB;    transmitters;    pulse generator;    synchronous delay;    FPGA;   

DOI  :  10.1587/elex.9.868

学科分类：电子、光学、磁材料

来源: Denshi Jouhou Tsuushin Gakkai

【 摘 要 】

References(9)This paper presents an architecture for generating UWB pulses with a high centre frequency accuracy. The architecture allows to generate frequencies twice that of the FPGA clock using synchronous delays and is implementable in all types of FPGA. With a FPGA clock of 150MHz, we generate RF pulse of 300MHz with a maximum fractional bandwidth of 30%. The architecture also allows pulse width increment in steps of the clock period.

【 授权许可】

Unknown