Efficient systolic modular multiplier/squarer for fast exponentiation over GF(2m)

IEICE Electronics Express

Se-Hyu Choi¹  Keon-Jik Lee¹ 

[1] School of Architectural, Civil, Environmental and Energy Engineering, Kyungpook National University

关键词: modular multiplication;    finite field arithmetic;    systolic array;   

DOI  :  10.1587/elex.12.20150222

学科分类：电子、光学、磁材料

来源: Denshi Jouhou Tsuushin Gakkai

【 摘 要 】

References(5)Using the concept of common components, this letter shows that field multiplication and squaring over GF(2m) can be efficiently combined, with little hardware overhead. The analysis results show that about 39.23% area-time (AT) complexity is improved when we employ the combined systolic multiplier/squarer instead of implementing the multiplier and the squarer separately in the least significant bit (LSB)-first exponentiation. The proposed architecture features regularity, unidirectional data flow, and local interconnection, and thus is well suited to VLSI implementation.

【 授权许可】

Unknown