SAR+ΔΣ ADCs with open-loop integrator using dynamic amplifier

IEICE Electronics Express

Akira Matsuzawa^1¹ 

[1] Department of Electrical and Electronic Engineering, Tokyo Institute of Technology^1

关键词: analog to digital converter;    SAR;    delta-sigma;    dynamic amplifier;    integrator;    low energy;   

DOI  :  10.1587/elex.15.20182002

学科分类：电子、光学、磁材料

来源: Denshi Jouhou Tsuushin Gakkai

【 摘 要 】

This paper proposes and discusses SAR+ΔΣADCs with open-loop integrators for low power, high speed, and low noise sensing systems. The integrator uses an open-loop architecture and dynamic amplifier to realize high speed and low power complete integration. Two prototype ADCs have been developed for general purpose and for CMOS image sensors. A high dynamic range of 84 dB and a high Schreier’s FoM of 173 dB have achieved. Furthermore, a high FoM over 170 dB is maintained across a wide range of sampling rate from 2.5 MS/s to 25 MS/s. The SAR+ΔΣADC for CMOS image sensors can reduce the noise down to 66 µV.

【 授权许可】

CC BY