Design of Linear Systolic Arrays for Matrix Multiplication

Advances in Electrical and Computer Engineering

MILOVANOVIC, E. I. ; STOJCEV, M. K. ; MILOVANOVIC, I. Z. ; NIKOLIC, T. R..

关键词: address generator units;    linear systolic arrays;    matrix multiplication;   

DOI  :  10.4316/AECE.2014.01006

学科分类：计算机科学（综合）

来源: Universitatea "Stefan cel Mare" din Suceava

【 摘 要 】

This paper presents architecture for matrix multiplication optimized to be integrated as an accelerator unit to a host computer. Two linear systolic arrays with unidirectional data flow (ULSA), used as hardware accelerators, where synthesized in this paper. The solution proposed here is designed to accelerate both the computation and communication by employing hardware address generator units (AGUs). The proposed design has been implemented on Xilinx Spartan-2E and Virtex4 FPGAs. In order to evaluate performance of the proposed solution, we have introduced quantitative and qualitative performance criteria. For the ULSA with n processing elements (PEs), the speed-up is O(n/2). Average gain factor of hardware AGUs is about 2.7, with hardware overhead of 0.6% for 32-bit PEs.

【 授权许可】

Unknown