Instruction-level Real-time Secure Processor Using an Error Correction Code

Advances in Electrical and Computer Engineering

YOON, S. M¹ 

关键词: secure processor;    security;    instruction;    correlation;    chain;   

DOI  :  10.4316/AECE.2015.03002

学科分类：计算机科学（综合）

来源: Universitatea "Stefan cel Mare" din Suceava

【 摘 要 】

In this paper, we present a processor that detects security-attacks at the instruction level by checking the integrity of instructions in real time. To confirm the integrity of the instructions, we generate a parity chain of instructions and check them at run time. The parity chain is generated using an error correction code used in a digital communication system, and the integrity checker has the same function as the error-detector module of the error correction code. This architecture can readily be applied to a general processor, because the checker is located between the processor core and the instruction memory. Compared with other cipher modules with the same key space, our instruction integrity checker achieves a faster check speed and occupies a smaller area.

【 授权许可】

Unknown