An energy-efficient parallel VLSI architecture for SVM classification

IEICE Electronics Express

Zhijian Chen¹  Yin Xu¹  Xiaoyan Xiang²  Jianyi Meng² 

[1] Institute of VLSI Design, Zhejiang University;State Key Laboratory of ASIC and System, Fudan University

关键词: SVM;    energy-efficient;    cost-reduced element;    partial parallel architecture;   

DOI  :  10.1587/elex.15.20180099

学科分类：电子、光学、磁材料

来源: Denshi Jouhou Tsuushin Gakkai

【 摘 要 】

This letter presents an energy-efficient VLSI architecture for SVM classification. Instead of accurate calculation, cost-reduced computing elements based on approximative techniques are designed to complete computation-intensive operations in the SVM-based classifier to save energy and resources. Besides, a partial parallel structure is applied to eliminate dimensional constraints for inputs of classifiers and balance between classification speed and energy consumption. We adopt 55-nm CMOS process to implement the proposed design. It occupies 0.0901 mm2 area and consumes 15.9 mW at operating frequency of 100 MHz and from an operating voltage of 1 V. Experiment shows that the design provides an area reduction by 41.5% and a significant saving in energy efficiency by 61.8% compared with the baseline model.

【 授权许可】

CC BY