A nanosecond-accuracy clock synchronization circuit for IEEE 1588-2008 using tapped delay lines

IEICE Electronics Express

Jiho Han¹  Changyong Shin² 

[1] Department of Electronics Engineering, Sun Moon Univ.;School of Mechanical and ICT Convergence Engineering, Sun Moon Univ.

关键词: clock synchronization;    IEEE 1588;    tapped delay lines;   

DOI  :  10.1587/elex.13.20160922

学科分类：电子、光学、磁材料

来源: Denshi Jouhou Tsuushin Gakkai

【 摘 要 】

This letter presents a high-accuracy clock synchronization circuit, which reduces the time error between the master and slave clocks to less than 1 ns. To suppress quantization errors resulted in generation of timestamps and pulse-per-second (PPS) signals, time-to-digital converters (TDC) and digital-to-time converters (DTC) have been implemented using tapped delay lines. The proposed scheme provides a cost-effective solution for applications of clock synchronization since it works on gigabit Ethernet using copper media (1000BASE-T) without any extra clock synthesis. Experimental results show that the two nodes over network share synchronized timing within the error between −0.74 ns and 0.89 ns.

【 授权许可】

CC BY