Design of memory efficient FIFO-based merge sorter

IEICE Electronics Express

Yong Ho Song¹  Youngil Kim¹  Seungdo Choi¹ 

[1] Department of Electronics and Computer Engineering, Hangyang University

关键词: sorting;    accelerator architectures;    FPGAs;   

DOI  :  10.1587/elex.15.20171272

学科分类：电子、光学、磁材料

来源: Denshi Jouhou Tsuushin Gakkai

【 摘 要 】

Sorting is an important operation used in various applications including image processing and databases. It represents a large portion of the total execution time of these applications. To improve the performance of sort operations, a dedicated hardware sorter can be used. When implemented in hardware, a FIFO-based merge sorters often shows excellent hardware resource utilization efficiency but requires high buffer memory usage. In this paper, we presents a cost-effective hardware architecture of a FIFO-based merge sorter. Our proposed architecture minimizes buffer memory requirement. We evaluate the design by implementing the architecture on an FPGA platform. FPGA synthesis results show that the proposed approach reduces the average flip-flop and LUT-RAM by 5% and 14%, respectively.

【 授权许可】

CC BY