Design of hardware accelerator for Lempel-Ziv 4 (LZ4) compression

IEICE Electronics Express

Seung Eun Lee¹  Sang Muk Lee¹  Jung Hwan Oh¹  Ji Kwang Kim¹  Ji Hoon Jang¹ 

[1] Dept. of Electronic Engineering, Seoul National University of Science and Technology

关键词: data compression;    LZ4;    hardware accelerator;    high throughput;   

DOI  :  10.1587/elex.14.20170399

学科分类：电子、光学、磁材料

来源: Denshi Jouhou Tsuushin Gakkai

【 摘 要 】

Hardware accelerators are being considered as important architectural components in the context of datacenter customization to achieve high performance and low power. Compression has played an important role in computer systems by enhancing storage and communication efficiency in the charge of extra computational cost. In this letter, we present a fully pipelined compression accelerator for the Lempel-Ziv (LZ) compression algorithm. The compression accelerator is verified by using FPGA and fabricated using 65 nm CMOS technology.

【 授权许可】

CC BY