A practical, low-overhead, one-cycle correction design method for variation-tolerant digital circuits

IEICE Electronics Express

Lin-lin Xie¹  Yong Hei¹  Jia Yuan¹  Shu-shan Qiao²  Yi Yu² 

[1] Institute of Microelctronics of Chinese Academy of Sciences;University of Chinese Academy of Sciences

关键词: AVS;    DVFS;    adaptive circuits;    EDAC;    time borrowing;    variation tolerance;   

DOI  :  10.1587/elex.14.20171202

学科分类：电子、光学、磁材料

来源: Denshi Jouhou Tsuushin Gakkai

【 摘 要 】

This paper presents a practical, low-overhead, one-cycle correction better-than-worst-case design method for ultra-low voltage digital circuits. Excessive design margin for PVT variation brought by traditional worst-case design method is eliminated. Proposed method is completely compatible with EDA tools. Considerable design efforts are relaxed compared with other variation-tolerant techniques. We have implemented our proposed technique on a 16 bits × 16 bits pipelined multiplier in SIMC 55 nm CMOS process. The experimental results show that our proposed technique can get about 59% energy efficiency improvements compared with operating in worst-case timing margin.

【 授权许可】

CC BY