CMOS realisation of analogue processor for early vision processing

Bulletin of the Polish Academy of Sciences. Technical Sciences

G. BlakiewiczDepartment of Microelectronic Systems, Gda?sk University of Technology, 11/12 Narutowicza St., 80-952 Gda?sk, PolandOther articles by this author:De Gruyter OnlineGoogle Scholar¹  S. Szczepa?skiDepartment of Microelectronic Systems, Gda?sk University of Technology, 11/12 Narutowicza St., 80-952 Gda?sk, PolandOther articles by this author:De Gruyter OnlineGoogle Scholar¹  R. PiotrowskiDepartment of Microelectronic Systems, Gda?sk University of Technology, 11/12 Narutowicza St., 80-952 Gda?sk, PolandOther articles by this author:De Gruyter OnlineGoogle Scholar¹  W. JendernalikDepartment of Microelectronic Systems, Gda?sk University of Technology, 11/12 Narutowicza St., 80-952 Gda?sk, PolandOther articles by this author:De Gruyter OnlineGoogle Scholar¹  J. JakuszDepartment of Microelectronic Systems, Gda?sk University of Technology, 11/12 Narutowicza St., 80-952 Gda?sk, PolandOther articles by this author:De Gruyter OnlineGoogle Scholar¹ 

[1] Department of Microelectronic Systems, Gda?sk University of Technology, 11/12 Narutowicza St., 80-952 Gda?sk, Poland

关键词: Keywords: CMOS imager;    analogue processor array;    smart sensor;    vision chip;   

DOI  :  10.2478/v10175-011-0018-x

学科分类：工程和技术（综合）

来源: Polska Akademia Nauk * Centrum Upowszechniania Nauki / Polish Academy of Sciences, Center for the Advancement of Science

【 摘 要 】

The architecture concept of a high-speed low-power analogue vision chip, which performs low-level real-time image algorithms is presented. The proof-of-concept prototype vision chip containing 32 × 32 photosensor array and 32 analogue processors is fabricated using a 0.35 μm CMOS technology. The prototype can be configured to register and process images with very high speed, reaching 2000 frames per second, or achieve very low power consumption, several μW. Finally, the experimental results are presented and discussed.

【 授权许可】

Unknown