Particle swarm optimisation driven low cost single event transient fault secured design during architectural synthesis

The Journal of Engineering

Deepak Kachave¹  Anirban Sengupta¹ 

[1] Discipline of Computer Science and Engineering, Indian Institute of Technology Indore, Indore, India

关键词: dual modular redundant;    area/delay overhead;    architectural synthesis;    area-delay constraints;    low-cost single event transient fault secured design;    particle swarm optimisation;    application specific datapath;    high-level synthesis;    DMR;   

DOI  :  10.1049/joe.2016.0378

学科分类：工程和技术（综合）

来源: IET

【 摘 要 】

Owing to aggressive shrinking in nanometre scale as well as faster devices, particle strike manifesting itself into transient fault spanning multiple cycle and multiple units will be the centre-focus of application specific datapath generated through high-level synthesis (HLS)/architectural synthesis. Addressing each problem above separately leads to large area/delay overhead; thus tackling both problems concurrently, leads to huge incurred overhead. To tackle this complex problem, this paper proposes a novel low cost particle swarm optimisation driven dual modular redundant (DMR) based HLS methodology for generation of a transient fault secured design secured against its temporal and spatial effects. The authors' approach provides a low cost optimised fault secured solution through a particle swarm optimisation exploration framework based on user area-delay constraints. Results indicated that proposed approach obtains an area overhead reduction of 34.08% and latency overhead reduction of 5.8% compared with a recent approach.

【 授权许可】

CC BY