Capacitive digital-to-analogue converters with least significant bit down in differential successive approximation register ADCs

The Journal of Engineering

Wai-Tung Ng³  Lei Sun³  Kong-Pang Pun⁵ 

[1] Computer Engineering, University of Toronto, 10 King'Department of Electrical &Department of Electronic Engineering, Chinese University of Hong Kong, Shatin, Hong Kong, N.T., People's College Road, Toronto, Canada;s Republic of China

关键词: CDAC;    unit capacitor;    logic circuits;    chip area;    least signihcant bit-down switching scheme;    DNL-INL performance;    switching energy;    capacitive digital-to-analogue converters;    differential successive approximation register ADC;   

DOI  :  10.1049/joe.2013.0219

学科分类：工程和技术（综合）

来源: IET

【 摘 要 】

This Letter proposes a least significant bit-down switching scheme in the capacitive digital-to-analogue converters (CDACs) of successive approximation register analog-to-digital converter (ADC). Under the same unit capacitor, the chip area and the switching energy are halved without increasing the complexity of logic circuits. Compared with conventional CDAC, when it is applied to one of the most efficient switching schemes, V cm-based structure, it achieves 93% less switching energy and 75% less chip area with the same differential non linearity (DNL)/integral non linearity (INL) performance.

【 授权许可】

CC BY