Double-Sharpened Decimation Filter Employing a Pre-droop Compensator for Multistandard Wireless Applications

ETRI Journal

关键词: sigma-delta;    sharpened filter;    decimation filter;    Cascaded integrator-comb;   

Others  :  1186128
DOI  :  10.4218/etrij.11.0110.0272

【 摘 要 】

This paper presents a double-sharpened decimation filter based on the application of a Kaiser and Hamming sharpening technique for multistandard wireless systems. The proposed double-sharpened decimation filter uses a pre-droop compensator which improves the passband response of a conventional cascaded integrator-comb filter so that it provides an efficient sharpening performance at half-speed with comparison to conventional sharpened filters. In this paper, the passband droop characteristics with compensation provides –1.6 dB for 1.25 MHz,–1.4 dB for 2.5 MHz, –1.3 dB for 5 MHz, and –1.0 dB for10 MHz bandwidths, respectively. These results demonstrate that the proposed double-sharpened decimation filter is suitable for multistandard wireless applications.

   

【 参考文献 】

• [1]C. Jeong, Y. Kim, and S. Kim, "Efficient Discrete-Time Bandpass Sigma-Delta Modulator and Digital I/Q Demodulator for Multistandard Wireless Applications," IEEE Trans. Consum. Electron., vol. 54, no. 1, Feb. 2008, pp. 25-32.
• [2]C. Jeong, Y.-J. Min, and S.-W. Kim, "Two-Stage Digital I/Q Demodulator Employing a Reconfigurable 16-Phase Down-Mixing Technique," IEICE Electron. Express, vol. 7, no. 3, Feb. 2010, pp. 177-183.
• [3]R.C. deLamare and R. Sampaio-Neto, "Adaptive Reduced-Rank MMSE Filtering with Interpolated FIR Filters and Adaptive Interpolators," IEEE Signal Process. Lett., vol. 12, no. 3, Mar. 2005, pp. 177-180.
• [4]R.C. deLamare and R. Sampaio-Neto, "Adaptive Reduced-Rank Processing Based on Joint and Iterative Interpolation, Decimation and Filtering," IEEE Trans. Signal Process., vol. 57, no. 7, July 2009, pp. 2503-2514.
• [5]A. Blad and O. Gustafsson, "Integer Linear Programming-Based Bit-Level Optimization for High-Speed FIR Decimation Filter Architectures," Circuits, Syst., Signal Process., vol. 29, no. 1, Feb. 2010, pp. 81-101.
• [6]A. Mora-Sanchez and D. Schroeder, "Decimation Filter in a 0.35 um Technology for a Multi-channel Biomedical Data Acquisition Chip," Proc. IBERCHIP Workshop, Bahia, Brazil, Mar. 2005, pp. 199-202.
• [7]M. Laddomada, "Design of Multistage Decimation Filters Using Cyclotomic Polynominals: Optimization and Design Issues," IEEE J. Solid-State Circuits, vol. 55, no. 7, Aug. 2008, pp. 1977-1987.
• [8]Q. Liu and J. Gao, "On Design of Efficient Comb Decimator with Improved Response for Sigma-Delta Analog-to-Digital Converters," Proc. ICISP, Tianjin, Oct. 2009, pp. 1-5.
• [9]E.B. Hogenauer, "An Economical Class of Digital Filters for Decimation and Interpolation," IEEE Trans. Acoust., Speech, Signal Process., vol. ASSP-29, no. 2, Apr. 1981, pp. 155-162.
• [10]M. Abbas, O. Gustafsson, and L. Wanhammar, "Power Estimation of Recursive and Non-recursive CIC Filters Implemented in Deep-Submicron Technology," Proc. IEEE ICGCS, Shanghai, China, June 2010.
• [11]Y. Gao, L. Jia, and H. Tenhunen, "A Fifth-Order Comb Decimation Filter for Multi-standard Transceiver Applications," Proc. IEEE ISCAS, Geneva, Switzerland, vol. 2, May 2000, pp. 1345-1348.
• [12]A.Y. Kwentus, Z. Jiang, and A.N. Willson, "Application of Filter Sharpening to Cascaded Integrator-Comb Decimation Filters," IEEE Trans. Signal Process., vol. 45, no. 2, Feb. 1997, pp. 457-467.
• [13]H. Aboushady et al., "Efficient Polyphase Decomposition of Comb Decimation Filters in ΣΔ Analog-to-Digital Converters," IEEE Trans. Circuits Syst. II, Analog Digit. Signal Process., vol. 48, no. 10, Oct. 2001, pp. 898-903.
• [14]L.L. Presti, "Efficient Modified-Sinc Filters for Sigma-Delta A/D Converters," IEEE Trans. Circuits Syst. II, Analog Digit. Signal Process., vol. 47, no. 11, Nov. 2000, pp. 1204-1213.
• [15]G. Stephen and R.W. Stewart, "Sharpening of Decimating CIC Filter," IEE Electron Lett., vol. 40, no. 21, Oct. 2004, pp. 1383-1384.
• [16]G.J. Dolecek and S.K. Mitra, "A New Two Stage Sharpened Comb Decimator," IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 52, no. 7, July 2005, pp. 1414-1420.
• [17]G.J. Delecek and F. Harris, "Design of Wideband Compensator for Digital IF Receiver," J. Elsevier Digital Signal Process., vol. 19, no. 5, Sept. 2009, pp. 827-837.
• [18]J.F. Kaiser and R.W. Hamming, "Sharpening the Response of a Symmetric Nonrecursive Filter," IEEE Trans. Acoust., Speech, Signal Process., vol. ASSP-25, no. 3, Oct. 1977, pp. 415-422.
• [19]F.J.T. Torres and G.J. Dolecek, "Compensated CIC-Cosine Decimation Filter," Proc. ISCIT, Sydney, Australia, Oct. 2007, pp. 256-259.
• [20]K.S. Yeung and S.C. Chan, "The Design and Multiplier-less Realization of Software Radio Receivers with Reduced System Delay," IEEE Trans. Circuits Syst. I: Reg. Papers, vol. 51, no. 12, Dec. 2004, pp. 2444-2459.
• [21]A.P. Chandrakasan and R.W. Brodersen, "Minimizing Power Consumption in Digital CMOS Circuits," Proc. IEEE, vol. 83, Apr. 1995, pp. 498-523.