Verification Platform with ARM- and DSP-Based Multiprocessor Architecture for DVB-TBaseband Receivers

ETRI Journal

关键词: crossbar switch;    communication interface;    pipelined scheduling;    DVB-T baseband receiver;    Multiprocessor SoC platform;   

Others  :  1185724
DOI  :  10.4218/etrij.08.0107.0129

【 摘 要 】

In this paper, we introduce a new verification platform with ARM- and DSP-based multiprocessor architecture. Its simple communication interface with a crossbar switch architecture is suitable for a heterogeneous multiprocessor platform. The platform is used to verify the function and performance of a DVB-T baseband receiver using hardware and software partitioning techniques with a seamless hardware/software co-verification tool. We present a dual-processor platform with an ARM926 and a Teak DSP, but it cannot satisfy the standard specification of EN 300 744 of DVB-T ETSI. Therefore, we propose a new multiprocessor strategy with an ARM926 and three Teak DSPs synchronized at 166 MHz to satisfy the required specification of DVB-T.

   

【 参考文献 】

• [1]P. Gerin, S. Yoo, G. Nicolescu and A. Jerraya, "Scalable and Flexible Cosimulation of SoC Designs with Heterogeneous Multi-processor Target Architectures," ASP-DAC, Feb. 2001, pp. 63?68.
• [2]I. Saastamoinen, D. Siguenza-Tortosa, and J. Nurmi, "Interconnect IP Node for Future Systems-on-Chip Designs," Proc. IEEE Workshop on Electronic Design, Test and Applications, Jan. 2002, pp. 116-120.
• [3]M. Dall’Osso, G. Biccari, L. Giovannini, D. Bertozzi, and L. Benini, "Xpipes: A Latency Insensitive Parameterized Network-on-Chip Architecture for Multi-processor SoCs," Proc. ICCD, Oct. 2003, pp. 536-539.
• [4]Sonics, "Sonics uNetworks Technical Overview," Jan. 2002. www.sonicsinc.com/sonics/support/documentation/whitepapers/data/Overview.pdf.
• [5]Opencore, "WISHBONE System-on-Chip (SoC) Interconnection Architecture for Portable IP Cores," Rev. B.3, 2002, http://www.opencores.org/.
• [6]L. Benini and D. Bertozzi, "Network-on-Chip Architectures and Design Methods," IEEE Proc. Computers and Digital Techniques, vol. 152, no. 2, Mar. 2005, pp. 261-272.
• [7]ETSI, "Digital Video Broadcasting (DVB): Framing Structure, Channel Coding and Modulation for Digital Terrestrial Television," EN 300 744, V1.4.1 Jan. 2001.
• [8]C. Pan, N. Bagherzadeh, A.H. Kamalizad, and A. Koohi, "Design and Analysis of a Programmable Single-Chip Architecture for DVB-T Base-Band Receiver," Design, Automation, and Test in Europe Conf. and Exhibition, 2003, pp. 468-473.
• [9]F. Frescur, S. Pielmeier, G. Reali, G. Baruffa, and S. Cacopardi, "DSP-Based OFDM Demodulator and Equalizer for Professional DVB-T Receivers," IEEE Trans. Broadcasting, vol. 45, no. 3, Sept. 1999, pp. 323?332.
• [10]J.Y. Chang, W.J. Kim, Y.H. Bae, J.H. Han, H.J. Cho, and H.B. Jung, "Performance Analysis for MPEG-4 Video Codec Based on On-Chip Network", ETRI Journal, vol. 27, no. 5, Oct. 2005, pp. 497-503.
• [11]F. Classen and H. Meyr, "Frequency Synchronization Algorithms for OFDM Systems Suitable for Communication over Frequency Selective Fading Channels," Proc. of VTC, 1994, pp. 1655-1659.
• [12]H.W. Lee, K.Y. Kim, and H.J. Choi,"An Efficient Frequency and Symbol Synchronization Structure for DVB-T System," Korea Institute of Communication Systems, vol. 27, no. 2, 2002.
• [13]J. Beek, M. Sandell, and P. Borjesson, "On Synchronization in OFDM Systems Using the Cyclic Prefix," Proc. of RVK (Radiovetenskaplig Konferens), 1996, pp. 663-667.
• [14]A. Niktash, H.T. Parizi, and N. Bagherzadeh, "Application of a Heterogeneous Reconfigurable Architecture to OFDM Wireless Systems," ISCAS, May 2007, pp. 27-30.