A Low-Spur CMOS PLL Using Differential Compensation Scheme

ETRI Journal

关键词: integrated circuit design;    transformer;    spur rejection;    voltage-controlled oscillator (VCO);    CMOS;    differentially-tuned;    Phase-locked loop (PLL);   

Others  :  1186320
DOI  :  10.4218/etrij.12.0111.0417

【 摘 要 】

This paper proposes LC voltage-controlled oscillator (VCO) phase-locked loop (PLL) and ring-VCO PLL topologies with low-phase noise. Differential control loops are used for the PLL locking through a symmetrical transformer-resonator or bilaterally controlled varactor pair. A differential compensation mechanism suppresses out-band spurious tones. The prototypes of the proposed PLL are implemented in a CMOS 65-nm or 45-nm process. The measured results of the LC-VCO PLL show operation frequencies of 3.5 GHz to 5.6 GHz, a phase noise of –118 dBc/Hz at a 1 MHz offset, and a spur rejection of 66 dBc, while dissipating 3.2 mA at a 1 V supply. The ring-VCO PLL shows a phase noise of –95 dBc/Hz at a 1 MHz offset, operation frequencies of 1.2 GHz to 2.04 GHz, and a spur rejection of 59 dBc, while dissipating 5.4 mA at a 1.1 V supply.

   

【 参考文献 】

• [1]A. Rao et al., “A 4–6.4 GHz LC PLL with Adaptive Bandwidth Control for a Forwarded Clock Link,” IEEE J. Solid-State Circuits, vol. 43, no. 9, Sept. 2008, pp. 2099-2108.
• [2]M. Brownlee et al., “A 0.5-GHz to 2.5-GHz PLL with Fully Differential Supply Regulating Tuning,” IEEE J. Solid-State Circuits, vol. 41, no. 12, Dec. 2006, pp. 2720-2728.
• [3]N. Da Dalt and C. Sandner, “A Subpicosecond Jitter PLL for Clock Generation in 0.12-µm Digital CMOS,” IEEE J. Solid-State Circuits, vol. 38, no. 7, July 2003, pp. 1275-1278.
• [4]N.H.W. Fong et al., “A 1-V 3.8–5.7-GHz Wide-Band VCO with Differentially Tuned Accumulation MOS Varactors for Common-Mode Noise Rejection in CMOS SOI Technology,” IEEE Trans. Micro. Theory Techniques, vol. 51, no. 8, Aug. 2003, pp. 1952-1959.
• [5]Z. Yang, Z. Tang, and H. Min, “A Fully Differential Charge Pump with Accurate Current Matching and Rail-to-Rail Common-Mode Feedback Circuit,” IEEE ISCAS 2008, pp. 448-451.
• [6]J.H. Kim et al., “A 44 GHz Differentially Tuned VCO with 4GHz Tuning Range in 0.12 m SOI CMOS,” IEEE Int. Solid-State Circuits Conf. Dig. Tech. Papers, 2005, pp. 416-417.
• [7]A. Swaminathan, K.J. Wang, and I. Galton, “A Wide-Bandwidth 2.4 GHz ISM Band Fractional-N PLL with Adaptive Phase Noise Cancellation,” IEEE J. Solid-State Circuits, vol. 42, no.12, Dec. 2007, pp. 2639-2650.
• [8]S.-J. Yun et al., “A Differentially-Tuned Voltage Controlled Oscillator Using Symmetric Transformer,” IEEE Microw. Wireless Compon. Lett., vol. 18, no. 7, July 2008, pp. 464-466.
• [9]S.J. Yun et al., “Differentially-Tuned Low-Spur PLL Using 65 nm CMOS Process,” Electron. Lett., vol. 47, no. 6, Mar. 2011, pp. 369-371.
• [10]S.J. Yun et al., “A 1mW Current-Reuse CMOS Differential LC-VCO with Low Phase Noise,” IEEE Int. Solid-State Circuits Conf. Dig. Tech. Papers, 2005, pp. 540-541.
• [11]C.-Y. Kuo, J.-Y. Chang, and S.-I. Liu, “A Spur-Reduction Technique for a 5-GHz Frequency Synthesizer,” IEEE Trans. Circuits Systems-I: Regular Papers, vol. 53, no. 3, Mar. 2006, pp. 526-533.
• [12]S. Cha, C. Jeong, and C. Yoo, “A Phase-Locked Loop with Embedded Analog-to-Digital Convertor for Digital Control,” ETRI J., vol. 29, no, 4, Aug. 2007, pp. 463-469.
• [13]Y.G. Pu et al., “Low-Power, All-Digital Phase-Locked Loop with a Wide-Range, High Resolution TDC,” ETRI J., vol. 33, no. 3, June 2011, pp. 366-373.