Simulated Fault Injection Using Simulator Modification Technique

ETRI Journal

关键词: system-on-a-chip;    Verilog simulation;    reliability;    Simulated fault injection;   

Others  :  1186157
DOI  :  10.4218/etrij.11.0110.0106

【 摘 要 】

In the current very deep submicron technology era, fault tolerant mechanisms perform an essential function to cope with the effects of soft errors. To evaluate the effectiveness of the fault tolerant mechanism, reliability engineers use simulated fault injections using either saboteur modules or mutants in the simulation model. However, the two methods suffer from both inefficiency in the simulation mechanism and difficulties with the experimental setups. To overcome these inefficiencies, we propose the Verilog-based simulated fault injection (VFI) technique. VFI has the following advantages. First, modification of the design model is unnecessary. Second, the fault injection simulation procedure is simple and efficient. Third, various types of fault injection experiments can be performed. To evaluate the effectiveness of the proposed methodology, we developed a VFI environment using the ICARUS Verilog Simulator. From the experimental results, we were able to qualitatively evaluate the reliability of the target simulation models and to assess the effectiveness of the employed fault-tolerance mechanisms.

   

【 参考文献 】

• [1]L. Anghel et al., "Multi-level Fault Effects Evaluation," Radiation Effects on Embedded System, Springer, 2007, pp. 69-88.
• [2]D.W. Lee and J.W. Na, "A Novel Simulation Fault Injection Method for Dependability Analysis," IEEE Design & Test Computers, vol. 26, no. 6, Nov. 2009, pp. 50-61.
• [3]Y. Yu and B.W. Johnson, "Fault Injection Techniques," in Fault Injection Techniques and Tools for Embedded Systems Reliability Evaluation, A. Benso and P. Prinetto, Eds., Kluwer Academic Publishers, 2003, pp. 7-39.
• [4]M.C. Hsueh, T.K. Tsai, and R.K. Iyer, "Fault Injection Techniques and Tools," Computer, vol. 30, no. 4, Apr. 1997, pp. 75-82.
• [5]D. Gil et al., "VHDL Simulation-Based Fault Injection Techniques," in Fault Injection Techniques and Tools for Embedded Systems Reliability Evaluation, A. Benso and P. Prinetto, Eds., Kluwer Academic Publishers, 2003, pp. 159-176.
• [6]P.S. Roop, A. Sowmya, and S. Ramesh, "Forced Simulation: A Technique for Automating Component Reuse in Embedded Systems," ACM Trans. Design Auto. Electron. Syst., vol. 6 no. 4, Oct. 2001, pp. 602-628.
• [7]W. Savage, J. Chilton, and R. Composano, "IP Reuse in the System on a Chip Era," Proc. 13th Int. Symp. Syst. Synthesis, Madrid, Spain, Sept. 2000, pp. 2-7.
• [8]"IEEE Standard for Verilog Hardware Description Language," IEEE Computer, Apr. 2006.
• [9]W.J. Koh, D.W. Lee, and J.W. Na, "Cost Efficient Fault Tolerant Dual Processor for Soft Errors," submitted for publication.
• [10]B.Y. Kim, "Base ARM Technical Report," Technical Report, Korea Aviation Univ., 2009.
• [11]S. Williams and M. Baxter, "Icarus Verilog: Open-Source Verilog More Than a Year Later," Linux J., vol. 2002, no. 99, Jul. 2002.
• [12]T.J. Slegel et al, "IBM’s S/390 G5 Microprocessor Design," IEEE Micro., vol. 19, no. 2, Mar/Apr. 1999, pp. 12-23.
• [13]H. Ando et al., "A 1.3-GHz Fifth-Generation SPARC64 Microprocessor," IEEE J. Solid State Circuits, vol. 38, no. 11, Nov. 2003, pp. 1896-1905.
• [14]M.R. Guthaus et al., "MiBench: A Free, Commercially Representative Embedded Benchmark Suite," IEEE 4th Annual Workshop Workload Characterization, Austin, TX, 2001, pp. 3-14.
• [15]D. Seal, ARM Architecture Reference Manual, Addison-Wesley Professional, 2001, pp. 2-9.
• [16]L. Li et al., "Toward Distributed Verilog Simulation," Int. J. Simulation Syst. Sci. Technol., vol. 4, no. 3-4, 2003, pp. 44-54.
• [17]L. Zhu et al., "Parallel Logic Simulation of Million-Gate VLSI Circuits," Proc. 13th IEEE Int. Symp. Modeling, Anal. Simulation Computer Telecom. Syst., GA, USA, Sept. 2005, pp. 521-524.
• [18]Shubu Mukherjee, Architecture Design for Soft Errors, Morgan Kaufmann Publishers, 2007, pp.149-150, 154.
• [19]C.T. Weaver et al., "Reducing the Soft-Error Rate of a High-Performance Microprocessor," IEEE Micro., vol. 24, no. 6, Nov.-Dec. 2004, pp. 30-37.